Interfacial Shearing Stresses and Warpage of Flip-Chip Packages: Application of Analytical Thermal Stress Modeling
Ability to relieve thermal stresses in, and thermally-induced warpage of, electronic packages is of obvious practical importance. This is particularly true for the today’s high-density package designs, such as flip-chip, fine-pitch ball-grid-array, fan-in and fan-out wafer level packages and 2.5D and 3D package designs, which are prone to elevated thermal stresses and bow (warpage). Finite-element analysis (FEA) is a commonly-used technique today for the prediction of stresses and warpage in IC packages. It is always advisable, however, to employ, in addition to the powerful and flexible FEA simulation technique, when seeking the induced stresses and deformations, the “old-fashioned” analytical (“mathematical”) modeling. Analytical modeling and FEA are based, as a rule, on different assumptions, and if good agreement between the analytical modeling and FEA data are found, then there is a good reason to believe that the obtained prediction is both accurate and trustworthy.